Conventional high speed memory circuits require sensing circuits (also referred to as sense amplifier circuit) to sense and amplify a small signal, which is supplied by a memory cell when selected for a read operation. The sensing circuits are designed so that the small signal is detected reliably during logic 0 or logic 1 read operation.
A conventional sense amplifier circuit can detect a differential voltage between two nodes close to a source voltage (Vpwr). The nodes pertain to bit lines (BL and BLB) of a memory circuit. The sense amplifier circuit outputs a logic 0 or logic 1 value, thereby indicating data inside a memory cell. Typically, latch based sense amplifiers are used to achieve high speed and low power while operating the memory cell.
Referring to FIG. 1, a conventional linear sense amplifier 100 is shown, which comprises a plurality of NMOS (N-channel Metal Oxide Semiconductor) input transistors 110, a plurality of PMOS (P-channel Metal Oxide Semiconductor) transistors 120 coupled to each other in a current mirror configuration and coupled to the plurality of NMOS input transistors 110, a sense enabling (enabling signal saen) NMOS transistor 130 coupled to the common node of the plurality of NMOS input transistors 110. An output terminal (dataout) of the sense amplifier 100 generates a logic 1 or logic 0 output signal. The plurality of NMOS input transistors 110 is fed with a differential signal (inp and inm). The linear sense amplifier 100 is powered by a higher voltage supply Vcc and is coupled to a grounded node Vss.
A disadvantage of the conventional linear sense amplifier is that it draws more current and is slower in terms of access time compared to a conventional latch amplifier (explained in the next paragraph) for a given supply current specification.
Referring to FIG. 2, a conventional latch based sense amplifier 200 is shown, which comprises a plurality of NMOS input transistors 210, a plurality of cross coupled PMOS transistors 220 (in a positive feedback arrangement) coupled to the plurality of NMOS input transistors 210 and a sense enabling NMOS transistor 230 coupled to a common node of the plurality of NMOS input transistors 210. An output terminal (dataout) of the sense amplifier 200 generates a logic 1 or logic 0 output signal. The plurality of NMOS input transistors 210 is fed with a differential signal (inp and inm). The linear sense amplifier 200 is powered by a higher voltage supply Vcc and is coupled to a grounded node Vss.
A disadvantage of the conventional latch based sense amplifier is that it is not suitable for measuring very low leakage current or differential signals because of its sensitivity to input differential (non-overlapping) signals at the time of turn on of the sense amplifier. If the sense timing is incorrect, the latch based sense amplifier fails to read correct data due to incorrect polarity at its input while turn-on of a memory cell. The sense differential generated solely by the leakage currents in the memory array is very small and it takes a long time to generate a reasonable differential. This means that the latch based sense amplifiers may read incorrect data if they are turned on without the correct differential at its inputs.
It is therefore desirable that a power efficient and high speed sense amplifier with memory leakage testing and read debug capability be provided.